Real Intent

Real Intent operates within the Electronic Design Automation (EDA) software sector, providing tools that accelerate early functional verification and advanced sign-off for digital designs. The company was established in 1998 by Prakash Narain and Rajiv Kumar. Initially, its focus was on formal verification products, but in 2010, the company pivoted towards static sign-off, which forms the core of its current offerings. The firm is backed by prominent investors, including Andy Bechtolsheim, a founder of Sun Microsystems.

Dr. Prakash Narain, the current President and CEO, brings extensive experience from his time at IBM, AMD, and Sun Microsystems, where he was deeply involved in IC design, CAD tool development, and verification methodologies. His doctoral research at the University of Illinois at Champaign-Urbana focused on algorithms for high-level testing and verification, a background that directly informs Real Intent's technological direction. The company's business model is centered on selling its specialized EDA software to major semiconductor companies worldwide. Its client base includes over 50 major players in industries such as mobile, networking, telecommunications, and display graphics. Customers have included notable companies like NVIDIA, Samsung, STMicroelectronics, and Western Digital.

Real Intent’s product portfolio is designed to eliminate complex failure modes in Systems-on-a-Chip (SoCs). The offerings are categorized into two main families: Ascent, for early functional verification before simulation, and Meridian, for advanced sign-off verification. These tools address specific challenges in chip design, including multi-mode clock domain crossing (CDC), reset domain crossing (RDC), RTL linting, hardware security, and glitch verification. The company's software is engineered to handle designs exceeding 1 billion gates with high performance and accuracy, a key differentiator in the market. By employing static technologies, the software accelerates the sign-off of RTL source code, a process that would be exceedingly time-consuming with traditional simulation methods.

Keywords: Electronic Design Automation, EDA, RTL analysis, functional verification, static sign-off, semiconductor, SoC design, clock domain crossing, CDC, reset domain crossing, RDC, formal verification, hardware security, integrated circuit design, design for test, DFT, chip design software, digital design, verification tools, gate-level verification