RapidStream

About RapidStream

RapidStream Design Automation, Inc. is a company operating in the electronic design automation (EDA) market, specifically targeting the complexities of Field-Programmable Gate Array (FPGA) design.

The company's foundation is built upon award-winning academic research conducted at the University of California, Los Angeles (UCLA). Licheng Guo, who earned his Ph.D. from UCLA in 2022, is a founder of RapidStream. His doctoral research, supervised by Professor Jason Cong, a notable academic and serial entrepreneur in the EDA field, led to the creation of the core technology. This research, which resulted in best paper awards at the prestigious FPGA conferences in 2021 and 2022, focused on co-optimizing high-level synthesis (HLS) and the physical design stages of FPGA development.

RapidStream's business is centered around a software framework designed to drastically reduce the long compilation times associated with FPGA programming. The technology employs a split compilation approach, which partitions the design to enable parallel placement and routing, a departure from the conventional sequential tool flows. This methodology has been shown to decrease compilation times by a factor of 5 to 7 and increase the operating frequency of the resulting hardware by up to 1.3 times compared to standard commercial toolchains. The company provides tools that take a high-level C/C++ description of a dataflow program and generate a fully placed and routed implementation for the FPGA.

The company's offerings include open-source tools such as RapidStream TAPA, a C++ framework for designing high-frequency FPGA dataflow accelerators. This suggests a business model that may involve providing enterprise-grade versions of their software, offering dedicated support, or providing consulting services to companies that utilize FPGAs for applications like large language model and genomics acceleration. Potential clients are businesses that rely on high-performance FPGA accelerators and are looking to shorten their development cycles and improve hardware performance.